GPU and processor
RAM and processor
CD/DVD drives and Processor
Harddisk and Processor
D. Harddisk and Processor
internal
external
software
all of above
Pipe-lining
Super-scaling
Parallel Computation
None of these
GPU and processor
RAM and processor
CD/DVD drives and Processor
Harddisk and Processor
Reduce the size of the object code.
Reduce the clock cycles for a programming task.
Be able to detect even the smallest of errors.
Be versatile.
SCSI bus
PCI bus
Multiple bus
Controllers
Register file
Set registers
Register Block
Map registers
Register
RAM
System heap
Cache
Standard Performance Evaluation Code.
Standard Processing Enhancement Corporation.
System Processing Enhancing Code.
System Performance Evaluation Corporation.
Temp
PC
Z
IR
None of these
Ultra SPARC 10
SUN II
SUN SPARC
after OP code in the instruction
in memory
in stack
in the CPU register
Super-scalar
ISA
ANSA
All of the above
32K
128K
64K
1M
microprocessor
ALU
monochip
control unit
bytes - bit- field - record - file - database
bit - bytes - record - field - file - database
bytes -bit - record - field - file - database
bit - bytes - fields - record - file - database
M-bus
IB bus
ISA
None of these
Increase in size of the registers
Reduction in the number of cycles for execution
Better Connectivity
None of these
American National Standard Interface
American National Standards Institute
American Network Standard Interfacing
American Network Security Interrupt
read
read and execute
execute
write
Bridge circuits
Speed enhancing circuitory
Buffer registers
Multiple Buses
Better compilation of the given piece of code.
Takes advantage of the type of processor and reduces its process time.
Does better memory managament.
Both a and c
simulator
interpreter
commander
compiler
Cost effective connectivity and speed
Fast data transfers
Cost effective connectivity and ease of attaching peripheral devices
None of these
SCSI bus
PCI bus
Rambus
Memory bus
A
B
Both take the same time
Insuffient information
8
10
11
12
By using overclocking method
Improving the IC technology of the logic circuits
Reducing the amount of processing done in one step
All of the above
the memory address of the RET instruction is transferred to the program counter
the information where the stack is iniatialized is transferred to the stack pointer
two data bytes stored in the top two locations of the stack are transferred to the stack pointer
two data bytes stored in the top two locations of the stack are transferred to the program counter
Cache
Registers
System stack
System Heap